G12 Verilog BCH ECC IP

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The G12 BCH IP is optimized around a 256B correction block and supports up to 16 bits of error correction.   This non-standard correction size can be useful for specialty applications requiring smaller block sizes.

G12 Features:

  • Optimized for 256B correction blocks
  • Dynamically variable block sizes (2-450 bytes)
  • Area can be optimized by specifying a maximum ECC level via parameter
  • Supports both single-channel and multiple channel configurations
  • Higher levels of ECC are available upon request
  • ECC IP delivered as Verilog source with SystemVerilog Assertions