G13/G13X Verilog BCH ECC IP

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The G13 and G13X families of IP are optimized around a 512B correction block typically used with NAND devices using 2KB and 4KB page sizes.  The primary difference is the maximum number of errors supported:

Historically, SLC NAND has required a single bit correction which was implemented using Hamming codes in software.  As SLC transitions to smaller geometries, NAND manufacturers required 4-bit correction and are moving to higher ECC levels as technology nodes progress.

By integrating Cyclic Design's G13 ECC IP, your existing controller hardware and software can be easily extended to support SLC NAND flash requiring higher levels of ECC with far less investment than developing ECC expertise in-house.  Cyclic Design provides the G13 in an off-the-shelf configuration that fits well into most controller architectures or can provide a customized IP delivery to match your specific controller's requirements.  Cyclic Design can also work with your engineers to address specific latency, bandwidth, or area requirements to provide an optimal ECC solution for your application.

Common G13/G13X Features:

  • Optimized for 512B correction blocks
  • Dynamically variable block sizes (2-900 bytes)
  • Area can be optimized by specifying a maximum ECC level via parameter
  • Supports both single-channel and multiple channel configurations
  • Higher levels of ECC are available upon request
  • ECC IP delivered as Verilog source with SystemVerilog Assertions