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Monday, 23 November 2009 15:32

Cyclic Design Releases Advanced BCH Error Correction IP for Next Generation NAND Flash Applications

Cyclic Design announces advanced BCH ECC, supporting the next generation flash memory devices that require higher levels of error correction codes (ECC). Companies can preserve their investment in existing NAND flash hardware and software solutions by upgrading to this ECC infrastructure.

Austin, TX - November 23, 2009 - Cyclic Design (cyclicdesign.com) has announced the availability of its BCH ECC solution for next-generation NAND flash controllers. This IP supports 1KB correction blocks with up to 32 bits of ECC per block, enabling support for NAND flash devices that will be on the market within the next year. With this IP, companies can preserve their investment in existing NAND flash hardware and software by upgrading only the error correction portion of their design instead of buying and integrating a new controller design.

Over the past several years, vendors have gradually increased the ECC capabilities in their NAND flash controllers to accommodate the ever-increasing bit error rates of NAND flash. Most controllers today support 16-bit corrections over 512 byte blocks, which is sufficient for today's MLC flash devices.

Next generation NAND flash, however, will require stronger error correction to maintain acceptable levels of data integrity. To accomplish this, error correction must be performed over 1KB data blocks with much higher levels of ECC - typically ECC24 or ECC28. The change in block size requires a full redesign of the ECC logic, which can be a daunting challenge for companies without ECC expertise.

According to Eric Deal, founder of Cyclic Design, "NAND controllers are typically integrated very tightly with other I/O logic, so it does not make sense to replace an existing solution with a brand new controller. Companies now have the option of replacing just the error correction logic, minimizing both hardware and software development costs."

Cyclic Design's IP is available in verilog and is designed for use in both standalone NAND flash controllers as well as high-performance SSD applications, where the error correction can be shared among several channels of NAND flash. It supports programmable selection of block sizes and ECC levels and is parametrized to support a variety of performance and ECC options. The design runs at 300 MHz in the TSMC 45nm LP process and is also compatible with FPGA applications.

About Cyclic Design, LLC
Cyclic Design provides IP and consulting services for the semiconductor industry. The company specializes in ECC and NAND flash technology but has a broad base of experience through its founder, Eric Deal, who has over 15 years of industry experience.

For additional information and data sheets on Cyclic Design ECC solutions, contact Eric Deal or visit http://cyclicdesign.com.

Contact:
Eric Deal, Founder/Consultant
Cyclic Design, LLC
512-200-2925 (512-200-CYCL)
http://cyclicdesign.com
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