Read address and control stable while ARVALID

This assertion checks that ARVALID remains asserted until ARREADY is asserted, and the address and control signals (ARADDR, ARID, ARPROT, ARLEN, ARSIZE, ARBURST, ARCACHE, ARLOCK) associated with the AR bus remain stable until ARREADY is asserted.

There are several ways of specifying this assertion:

• Initiate a new check for every ARVALID,
• Initiate a check for each cycle that ARVALID is asserted without ARREADY, the controls remain stable the next cycle
• Initiate a check only when ARVALID is asserted and ARREADY is not asserted, and specify the conditions until ARREADY is asserted.

For this example, the third version is used to demonstrate the use of $rose() and the THROUGHOUT operator.

This assertion is triggered when ARVALID==1 and ARREADY==0 (non-acceptance of a read address).