Assertions in the Design Process

Implementing assertions within a design requires a conscious decision on the part of the designer to view the design process differently. Typically, designers approach a design in four stages:

1. Gain an understanding of the requirements of the design/algorithm,
2. Design RTL to implement a solution,
3. Perform some simple testing to verify basic functionality.
4. Debug test failures found by verification engineer

There may be variations to the process, such as creating a micro-architectural specification, but these additional steps generally fall into one of the above categories. Adding assertions, however, requires an additional step, which probably explains why designers haven't readily adopted assertion use.

1. Gain an understanding of the requirements of the design/algorithm,
2. Design RTL to implement a solution,
3. Add SystemVerilog Assertions (SVA)
4. Perform some simple testing to verify basic functionality.
5. Debug test failures found by verification engineer

As designers begin to understand the power of assertions, they will readily adopt them if for no other reason that pure selfishness: spending time creating assertions minimizes time spent debugging later.