A Different Mindset

Adding assertions requires the designer to think of the design from a different point of view. Instead of viewing signals as the implementation of a solution, designers must step back and think about what rules the design, bus/signal protocols, or usage model impose on these signals. These rules must then be coded in an assertion language such as the SystemVerilog Assertion language (SVA), in order to capture the behavior of individual signals or the interaction of several related signals.

It is important to note that assertions should not simply recreate rules forced on signals by a particular implementation. For instance, coding an assertion to recreate the transitions in a state machine is probably not terribly useful. However, coding assertions relating events occurring at a module's interface to the behavior of a state machine can be very powerful.

In order to focus on the process of developing assertions, this paper will focus on creating a simple subset of assertions for ARM's AXI bus interface. In doing this, we simplify the assertion writing process since assertions will be written for a well-known protocol, and we can use the AXI specification as our list of requirements.