Cyclic Design Verilog BCH ECC IP
Cyclic Design provides highly optimized and flexible BCH Error Correction IP in Verilog for both SLC and MLC NAND flash applications. The designs are highly modular and support both high performance and low area applications in both SOC and FPGA architectures. The IP includes over 60 SVA assertions, ensuring proper functionality and integration of the IP in a customer's controller.
Cyclic Design provides Verilog BCH ECC IP based on the following cores:
- G12 - Optimized for 256B correction blocks
- G13/G13X - Optimized for 512B correction blocks
- G14/G14X - Optimized for 1KB correction blocks
- G15 - Optimized for 2KB correction blocks
Each of the BCH ECC IP Cores shares a common interface to allow drop-in upgrades and can be customized to meet the specific requirements of your particular application.